1. Field of the Invention
The embodiments discussed herein relate to a semiconductor device and method of manufacturing a semiconductor device used as a switching device formed on a silicon carbide substrate.
2. Description of the Related Art
FIG. 13 is a cross-sectional view of an N-channel MOSFET that is a conventional switching device formed of silicon carbide. On a front surface side of an N-type silicon carbide (hereinafter, SiC) substrate 1, an N-type SiC layer 2 is formed and in a surface layer of the N-type SiC layer 2, plural P-type regions 3 are formed. In a surface layer of the P-type region 3, an N-type source region 4 and a P contact region 5 are formed. On a surface of the P-type region 3 and the N-type SiC layer 2 between N-type source regions 4, a gate electrode 7 is formed via a gate insulating film 6. On a surface of the gate electrode 7, an interlayer insulating film 8 is formed. On a surface of the N-type source region 4 and the P contact region 5, a first source electrode 9 is formed using nickel (Ni), and on a surface of the first source electrode 9 and the interlayer insulating film 8, a second source electrode 10 is formed. On a back surface side of the N-type SiC substrate 1, a drain electrode 11 is formed.
FIG. 14 is a cross-sectional view of a conventional N-channel MOSFET formed using a P-type SiC layer on a surface. On a front surface side of the N-type SiC substrate 1, the N-type SiC layer 2 is formed and in a surface layer of the N-type SiC layer 2, plural P-type regions 12 are formed. In a surface layer of the P-type region 12, a P-type SiC layer 13 is formed. On the N-type SiC layer 2 where no P-type region 12 is formed, an N-type region 14 is formed in the P-type SiC layer 13 and in the surface of the P-type SiC layer 13, the N-type source region 4 and the P contact region 5 are formed. On a surface of the N-type SiC layer 2 and the P-type SiC layer 13 between N-type source regions 4, the gate electrode 7 is formed via the gate insulating film 6. On a surface of the gate electrode 7, the interlayer insulating film 8 is formed. On the surface of the N-type source region 4 and the P contact region 5, the first source electrode 9 is formed using Ni, and on the surface of the first source electrode 9 and the interlayer insulating film 8, the second source electrode 10 is formed. On the back surface side of the N-type SiC substrate 1, the drain electrode 11 is formed.
In the MOSFETs of the structures depicted in FIGS. 13 and 14, when positive voltage relative to the first source electrode 9 is applied to the drain electrode 11 and voltage less than the gate threshold voltage is applied to the gate electrode 7, a PN junction between the P-type region 3 and the N-type SiC layer 2 or the P-type SiC layer 13 and the N-type region 14 is reverse biased and therefore, current does not flow. On the other hand, when voltage equal to or higher than the gate threshold is applied to the gate electrode 7, at the surface of the P-type SiC layer 13 of the P-type region 3 directly under the gate electrode 7, an inversion layer is formed, whereby current flows, enabling switching operation of the MOSFET by the voltage applied to the gate electrode 7 (for example refer to Japanese Patent Application Laid-Open Publication No. 2013-058603).